For high-speed RFID production, the fastest inline testers combine very low per-tag time with multi-lane parallelism. The CISC RAIN/NFC Xplorer Inline reaches an average of ~130,000 units per hour with instantaneous peaks up to 300,000 UPH, functional test points as fast as ~4 ms, web speeds up to 200 m/min (650 ft/min), and up to 12 simultaneous lanes. When a tag is also encoded and locked, all three operations run in a single pass — a combined cycle of roughly 15–30 ms depending on chip type and EPC length — instead of at separate stations.
„Fastest“ is a fair question to ask, but the honest answer is that a single headline UPH number can mislead. Real production throughput is the product of several factors, and a system that wins on one can lose on another. This article explains what actually determines inline-tester speed, gives the concrete figures that matter, and shows how to compare systems on production reality rather than a brochure number.
What is RAIN RFID?
What determines RFID inline-tester throughput?
- Test time per tag. The per-unit time to read, verify and (if required) encode and lock a tag. This is the system’s intrinsic speed. Lower is better, and it scales with how many test points and operations you ask for.
- Number of lanes. Testing tags in parallel multiplies throughput. A system that tests one lane at a time is fundamentally slower than one that tests many — which is why multi-lane capability dominates the UPH figure on wide webs.
- Pitch. The distance between tags on the web. Tighter pitch means more tags per metre, allowing faster processing cycles and better efficiency at a given web speed.
- Inlay width. Wider inlays fit fewer lanes across the web, reducing parallel testing and total UPH. The per-tag speed is unchanged; the number of parallel tags is what drops.
- Chip type. Different chip generations and commands vary in performance — the chip largely determines how fast data can be written or locked during production.
The practical implication: a credible comparison fixes the chip, inlay and pitch, and then asks how much throughput the tester delivers. CISC’s own design philosophy is built around this point — „Your production will not be slowed down by our system“ — meaning the line should be governed by the chip and the web, not the tester.
The figures that matter
For the CISC RAIN/NFC Xplorer Inline, the headline performance specification is:
| Specification | Figure |
| Average throughput | ~130,000 UPH |
| Peak (instantaneous) throughput | up to 300,000 UPH |
| Ultra-fast functional test time | < 4 ms (Go/No-Go test point — test only) |
| Combined test + encode + lock cycle | ~15–30 ms (chip- and EPC-length-dependent) |
| Web / line speed | up to 200 m/min (650 ft/min) |
| Lanes (parallel) | up to 12 |
| Operating mode | testing + encoding + locking in a single step (single pass) |
| Frequency (RAIN) | 800 MHz – 1 GHz |
| TX power range | −10 dBm to +28 dBm |
| Sensitivity | up to −80 dBm |
| Integration | hybrid or standalone; UART, GUI or API |
| Security | crypto/encryption for RAIN & NFC |
The NFC Xplorer Inline complements this with a test speed of ~100,000 UPH, full support for class 1–6 tags, variable H-field strength, read/write encoding and personalisation, and support for ISO/IEC 14443 A+B and 15693 — with the same single-step test-encode-lock philosophy.
Test-time detail
Because per-tag time scales with the operations requested, it helps to see the breakdown:
| Test mode | Typical time |
| 1 test point (Go/No-Go) | ~4 ms |
| 1 test point (Read EPC) | ~5 ms |
| 1 test point (Read TID) | ~9 ms |
| 3 test points (Read EPC) | ~15 ms |
| Write EPC (96-bit) | ~21 ms |
| Write EPC (96-bit) + Lock | ~26 ms |
Figures depend on chip type and configuration. The important property is linear, predictable scaling, so integrators can estimate achievable UPH before committing.
How CISC maximises each speed lever
Mapping the five throughput factors onto the CISC architecture shows where the speed comes from:
- Test time: test points as fast as ~4 ms, with linear scaling so adding test points has a known, bounded cost.
- Lanes: up to 12 simultaneous lanes, dividing per-tag cycle time across the web to reach high aggregate UPH.
- Pitch & inlay width: the largest antenna portfolio on the market, plus custom antenna designs on request, so the antenna can be matched to the inlay geometry rather than forcing a compromise — directly protecting UPH on awkward inlay widths.
- Chip type: broad chip support with chip-specific write/lock timing already characterised (e.g. the test-speed table above), so performance is predictable across chip generations.
The combination — fast per-tag time and up to 12 lanes and antenna matching and single-step operation — is what lets the system keep the line running at the chip-and-web limit rather than the tester limit.
Don’t forget: speed is only useful with 100% quality
The reason inline testing exists is to deliver 100% quality at production speed — not to trade one for the other. A fast tester that lets defects through has simply found a faster way to ship bad tags. The CISC value proposition pairs the throughput figures above with full single-step verification, encoding read-back, locking and a per-tag test record, so high speed and complete quality assurance are delivered together rather than as a trade-off.
Frequently Asked Questions
The fastest inline testers combine low per-tag time with multi-lane parallelism. The CISC RAIN/NFC Xplorer Inline averages ~130,000 UPH with instantaneous peaks up to 300,000 UPH, functional test points as fast as ~4 ms (testing only; a combined test-encode-lock cycle runs roughly 15–30 ms), and up to 12 simultaneous lanes.
A high-end inline system such as the CISC Xplorer Inline averages around 130,000 units per hour, with instantaneous peaks up to 300,000 UPH, depending on chip type, lane count, pitch and inlay width.
Five factors: per-tag test time, number of lanes, pitch (tag spacing), inlay width and chip type. Wider inlays reduce lane count; tighter pitch increases tags per metre; the chip sets write/lock speed.
The CISC NFC Xplorer Inline runs at a test speed of about 100,000 UPH, supports class 1–6 tags and ISO/IEC 14443 A+B and 15693, and performs encoding, testing and locking in one continuous process.
No. Inline testing exists to deliver 100% quality at production speed. The CISC system pairs high throughput with single-step test, encode-verify, lock and a per-tag record, so speed and quality assurance are delivered together.
Key Takeaways
- Real inline throughput depends on five factors: test time, lanes, pitch, inlay width and chip type — not a single headline number.
- The CISC RAIN/NFC Xplorer Inline averages ~130,000 UPH (peaks up to 300,000 UPH), with ~4 ms functional test points (a full test-encode-lock cycle is ~15–30 ms), up to 12 lanes and up to 200 m/min.
- The NFC variant runs ~100,000 UPH with class 1–6 support and ISO/IEC 14443/15693 conformance.
- CISC protects throughput across difficult inlay geometries with the market’s largest antenna portfolio and custom antenna design.
- Speed is only valuable alongside 100% quality — which single-step test, encode and lock delivers in the same pass.
Want a throughput estimate for your exact chip, inlay and pitch? Book a demo and a CISC engineer will model your achievable UPH.